Senior Physical Design Engineer

Location: Barcelona
VISA sponsorship provided if needed
Relocation help
Up to 80K according seniority

Role Overview

The company is seeking experienced professionals with strong expertise in synthesis, place & route (P&R) flows, floorplanning, and wire planning. A background in tape-out processes is essential, and familiarity with clock tree synthesis (CTS) — including custom clock tree design — is highly valued. Proficiency in netlist power analysis tools such as PrimeTime PX will also be a key factor for success in this role.

The selected candidate will collaborate closely with the floorplanning team on advanced technology nodes, developing synthesis and P&R flows, integrating custom blocks, and performing power analysis on the resulting netlists.

Requirements

• Bachelor’s, Master’s, or PhD in Computer Science or a related discipline
  
• 7+ years of industry experience in ASIC/SoC physical design
  
• At least two successful tape-outs
  
• Hands-on experience with EDA tools from Synopsys, Cadence, or Mentor
  
• Scripting skills (Tcl) for automation and flow optimization
  
• Solid understanding of physical design verification and sign-off methodologies, including timing closure, DRC, and LVS checks
  
• Knowledge of DFT techniques and Tessent flows is considered an advantage